Memory Explained

The CPU post gave programs a place to run but nowhere to live: registers hold a few dozen values, and that is all. The digital logic post showed how a flip-flop holds one bit. This post scales that bit up to gigabytes. We will look at the cells that store bits, the addresses that find them, the two great families of memory in a running machine, the three numbers that help compare memory systems, the bus that connects memory to the processor, and the hierarchy that reconciles speed with size.

Memory cells: holding one bit

Computer memory¹ is, at its lowest level, built from tiny circuits or physical structures that store bits, called memory cells. The machine needs billions of them, so the design of one cell, multiplied billions of times, decides the character of the whole memory.

There are two classic answers. An SRAM cell² (static RAM) can be understood as a small latch-like circuit: feedback holds the bit steady for as long as the power is on. A classic design uses six transistors per bit, which makes each cell fast and simple to use but physically large. A DRAM cell³ (dynamic RAM) takes the opposite trade: one transistor plus one tiny capacitor, where the bit lives as electrical charge. The cell is far smaller and cheaper, but the charge leaks away over milliseconds, so the memory must periodically refresh the cells before their charge leaks away (a background chore called refresh) just to remember.

Speed and simplicity versus density and cost. That single tradeoff explains why a machine contains both kinds, as we will see.

Addresses: every byte has a number

A pile of cells is useless without a way to name each one. That name is the memory address⁴: a number identifying a location, much like a house number on a street. On modern machines memory is byte-addressable, meaning each address identifies one byte (eight bits), and multi-byte values occupy consecutive addresses.

With n address bits you can name 2^n locations: 32 bits can address 2^32 bytes, or 4 GiB; 64 bits could in principle address 2^64 bytes, far more than any machine holds, so real chips use fewer address bits in practice. A program’s pointers and the stack pointer from the CPU post are all values used to identify memory locations.

RAM: the workbench

Random-access memory⁵ is the memory holding the running programs and their data: code loaded from storage, the heap, the call stack. “Random access” means any address can be read or written directly, in roughly the same time, unlike a tape, where reaching data means winding past everything before it.

Two traits define RAM’s role. It is the CPU’s primary partner: fast enough to provide large working storage, while caches hide much of its latency, and large enough (gigabytes) to hold everything currently running. And in its usual DRAM form, it forgets everything when the power goes out. That is why unsaved work vanishes in a blackout and why every boot starts by loading the operating system from storage into RAM again.

ROM: memory that remembers

Read-only memory⁶ is the mirror image: memory optimized for keeping its contents without power rather than for being rewritten. The classic use is firmware: the first instructions a machine executes on power-up, which must already be there before anything can be loaded from storage.

Strictly read-only chips are mostly history. Modern firmware lives in rewritable non-volatile memory⁷ such as flash memory⁸, which keeps its bits without power yet can be reprogrammed (slowly, in large blocks) when the firmware needs updating. The deep story of persistent storage (how flash, SSDs, and disks keep data for years) belongs to the storage post; here ROM matters as one idea: some memory’s job is to remember through the dark.

SRAM vs DRAM: why both exist

Put the two families side by side and the machine’s design reads as a compromise:

              SRAM                  DRAM
cell          latch-like, ~6        1 transistor +
              transistors           1 capacitor
size          large                 tiny
speed         very fast             slower
refresh       none needed           constant refresh
cost/bit      expensive             cheap
used for      caches                  main memory

SRAM is fast but hungry for silicon area; DRAM is dense but slower and needs refresh machinery. So architects spend SRAM where speed matters most (tiny quantities near the CPU) and DRAM where capacity matters most (gigabytes of working space). Neither technology wins outright. The hierarchy below exists precisely because no single cell type is fast, dense, and cheap at once.

Volatile vs non-volatile: the power test

The simplest classification of all: cut the power. If the bits survive, the memory is non-volatile⁷ (ROM, flash, disks); if they vanish, it is volatile (SRAM, DRAM in normal operation).

The running machine needs both. Volatile memory holds work in progress at high speed; non-volatile memory holds everything worth keeping (programs, documents, the operating system itself) across power cycles. Booting is the daily migration between the two: copying a working set from the non-volatile world into the volatile one.

Three numbers: capacity, latency, bandwidth

Three numbers are especially useful when comparing memory systems:

• Capacity: how much it holds. Registers hold tiny amounts of data, caches range from kilobytes to tens of megabytes, and main memory is measured in gigabytes.
• Latency: how long one access takes, usually in nanoseconds. Register accesses can take only a fraction of a nanosecond; fast caches can respond in around a nanosecond; main memory typically takes tens of nanoseconds⁹. Latency is the delay before the first byte arrives.
• Bandwidth: how much data arrives per second once flowing, usually in gigabytes per second. A modern memory channel moves on the order of tens of gigabytes per second. Bandwidth is the width of the pipe; latency is the length.

Latency and bandwidth are independent virtues. A sports car (low latency) delivers one passenger quickly; a train (high bandwidth) delivers hundreds slowly. Fetching one pointer chases latency; streaming a video frame rewards bandwidth. Performance work is largely the art of caring about the right one.

The memory bus: talking to RAM

Registers live inside the CPU, but main memory sits apart on the motherboard (or in the same package), so the processor reaches it through shared wires called the bus¹⁰. Conceptually three groups of signals cooperate:

CPU -------- address bus (which location?) -------> memory
CPU <------> data bus (the bytes themselves) <----> memory
CPU -------- control lines (read? write? when?) --> memory

To read, the CPU puts an address on the address bus, raises the read signal, waits, and collects the bytes arriving on the data bus. A 64-bit data path can transfer 8 bytes per transfer. Modern main memory transfers on both edges of its clock (the DDR in DDR4/DDR5 memory), doubling the transfers per tick, but the conversation keeps this same shape: ask by address, answer with data.

The memory hierarchy: pick two of fast, big, cheap

No single memory is the fastest, the largest, and the cheapest, so machines stack several into a memory hierarchy¹¹:

registers  (bytes,      sub-nanosecond, managed by compiler/program)
    ↓
caches     (KB–MB,      ~1 ns,  SRAM, managed by hardware)
    ↓
main memory (GB,        tens of ns, DRAM)
    ↓
storage    (TB,         microseconds–milliseconds, non-volatile)

The principle that makes this stack work is locality: programs tend to reuse the same data and instructions (temporal locality) and to touch neighboring addresses together (spatial locality). So hardware automatically keeps copies of recently and nearby used data in small fast levels (caches¹²), where most accesses hit, while the rare miss pays a trip down the ladder. Registers are managed explicitly by compiled code; caches are managed invisibly by hardware, tracking which copies are valid and fetching whole blocks (cache lines, typically 64 bytes) at a time.

This is also where the earlier posts connect: a register is flip-flops the program names directly; a cache is SRAM the hardware manages silently; main memory is DRAM used as the machine’s large working space. Same bits, different managers.

The big picture

Cells hold bits; addresses name bytes; RAM hosts work in progress while ROM remembers through power loss; SRAM buys speed and DRAM buys density; capacity, latency, and bandwidth help compare every level; the bus carries the conversation; and the hierarchy (registers, caches, main memory, storage) keeps the fastest levels fed with what locality predicts the CPU will want next.

What the hierarchy pushes downward is the next post’s subject: the non-volatile world where data rests for years: how flash cells, SSDs, and disks trade speed for persistence, and what that costs.

Footnotes

1. Computer memory - Wikipedia

2. Static random-access memory - Wikipedia

3. Dynamic random-access memory - Wikipedia

4. Memory address - Wikipedia

5. Random-access memory - Wikipedia

6. Read-only memory - Wikipedia

7. Non-volatile memory - Wikipedia

8. Flash memory - Wikipedia

9. CAS latency - Wikipedia

10. Bus (computing) - Wikipedia

11. Memory hierarchy - Wikipedia

12. Cache (computing) - Wikipedia