Table of Contents
Part of the series:Computers
The CPU post treated the ALU and the control unit as given: boxes that add, compare, and orchestrate. This post opens those boxes. We will build upward from the humblest component - a switch - through the mathematics of true and false, the gates that embody it, the circuits that compute and remember, and finally the ladder that reaches back up to the processor.
The transistor: a switch, nothing more
At the bottom there is no Boolean logic, only physics. A transistor1 is an electrically controlled switch: a small voltage on one terminal decides whether current flows between the other two. On means current can flow; off means it is largely blocked.
Everything else in this post is a consequence of that one behavior plus a convention from the previous post: interpret a high voltage as 1 and a low voltage as 0. Billions of such switches, etched into silicon and wired together, become a machine that computes. You do not need the semiconductor physics to continue - only the mental model of a switch being controlled billions of times per second.
Boolean logic: the math of true and false
Switches need a mathematics, and it is Boolean algebra2: a system with only two values, 0 (false) and 1 (true), and three fundamental operations:
- AND (
A · B):1only if both inputs are1. - OR (
A + B):1if at least one input is1. - NOT (
¬A): flips the value -¬0 = 1,¬1 = 0.
Two derived operations appear so often they earned their own names: XOR (exclusive OR - 1 when the inputs differ) and the negated pair NAND (NOT AND) and NOR (NOT OR). NAND is special for a practical reason: any Boolean function can be built from NAND gates alone (NOR shares this property). Chip designers love that - master one gate type, build everything.
The gates: logic made physical
A logic gate3 is the physical embodiment of a Boolean operation: a handful of transistors wired so the output voltage follows the operation’s rule. Each gate is fully described by its truth table4: every input combination and the resulting output.
AND, OR, and NOT:
AND OR NOT
A B | Q A B | Q A | Q
0 0 | 0 0 0 | 0 0 | 1
0 1 | 0 0 1 | 1 1 | 0
1 0 | 0 1 0 | 1
1 1 | 1 1 1 | 1XOR, NAND, and NOR5:
XOR NAND NOR
A B | Q A B | Q A B | Q
0 0 | 0 0 0 | 1 0 0 | 1
0 1 | 1 0 1 | 1 0 1 | 0
1 0 | 1 1 0 | 1 1 0 | 0
1 1 | 0 1 1 | 0 1 1 | 0Read XOR as “are they different?” and NAND as “not both.” Once you can read these tables, you have the basic vocabulary for reading digital circuits: gates wired together.
Combinational logic: circuits without memory
Wire gates together with no loops and you get combinational logic: the output depends only on the current inputs. Same inputs, same output, every time. Three such circuits do most of the computational work.
Adders: arithmetic from XOR
An adder6 adds binary numbers, exactly the addition from the information-representation post. Start with one column: a half adder takes bits A and B and produces a sum bit and a carry bit. The truth table reveals the gates hiding inside - the sum is A XOR B, the carry is A AND B.
A full adder adds three bits - A, B, and a carry-in from the less significant column - producing sum and carry-out:
A B Cin | Sum Cout
0 0 0 | 0 0
0 0 1 | 1 0
0 1 0 | 1 0
0 1 1 | 0 1
1 0 0 | 1 0
1 0 1 | 0 1
1 1 0 | 0 1
1 1 1 | 1 1Sum is A XOR B XOR Cin; carry-out is 1 whenever at least two inputs are 1 (the majority function). Chain eight full adders, feeding each carry-out into the next carry-in - a ripple-carry adder - and you add two bytes. Real chips use faster carry schemes, but the basic idea is identical: gates adding columns, with carries propagating from one bit position to the next.
Multiplexers: choosing between inputs
A multiplexer7 (mux) is a controlled selector. A 2-to-1 mux takes two data inputs (D0, D1), one select line S, and outputs whichever input S names:
S | Q
0 | D0
1 | D1Behind it: Q = (D0 AND NOT S) OR (D1 AND S). Widen the idea to 4, 8, or 32 inputs with more select bits and you have the circuit behind register-file reads, ALU operand selection, and other places where the machine must pick one signal among many.
Decoders: turning numbers into selections
A decoder8 does the inverse: an n-bit input activates exactly one of 2^n outputs. A 2-to-4 decoder:
A1 A0 | Y0 Y1 Y2 Y3
0 0 | 1 0 0 0
0 1 | 0 1 0 0
1 0 | 0 0 1 0
1 1 | 0 0 0 1This is how an address becomes an action: a decoder can turn a binary selection into one active output - for example, selecting a register or enabling one component of a circuit. The control unit from the CPU post can be understood, at a high level, as logic that decodes instruction bits into control signals.
Sequential logic: circuits with memory
Combinational circuits forget - cut the inputs and the answer vanishes. Sequential logic9 adds feedback: outputs looped back as inputs, so the circuit remembers what happened before.
Flip-flops: one bit that stays put
A latch uses feedback to hold a bit. An edge-triggered D flip-flop10 adds clocked behavior and becomes a fundamental building block of digital storage: on each rising edge of its clock input, it copies D to Q and holds it until the next edge.
D flip-flop (captures D on clock rise ↑):
D | CLK | Q (after)
0 | ↑ | 0
1 | ↑ | 1
x | 0 | holds
x | 1 | holds (no edge)Between edges the output ignores the input completely. That indifference is the whole point: it freezes time into discrete steps.
Registers: bits in formation
Put eight D flip-flops side by side, feed them the same clock, and you have an 8-bit register11: the storage element the CPU post called the processor’s workbench. A 64-bit register is sixty-four flip-flops ticking as one. Add multiplexers to select which register to read, and a decoder to select which register is enabled for writing, and you have a register file.
The clock: everyone marches together
The clock signal12 is a metronome: a square wave ticking billions of times per second. It does not compute anything. It solves a coordination problem - guaranteeing every flip-flop in the chip captures its input at the same agreed instant, after all combinational ripples have settled.
That constraint sets the chip’s speed limit: the clock period must be long enough for signals to propagate through the slowest relevant combinational path between sequential elements. Make the clock faster than the logic can settle and the receiving elements may capture incorrect values. Clock speed in gigahertz, pipelining, and most of CPU performance engineering are footnotes to this one rule.
The big picture
The full ladder, bottom to top:
transistors
↓
logic gates
↓
circuits
↓
adders / multiplexers / decoders / registers
↓
ALU
↓
CPUTransistors switch. Gates compute truth functions. Combinational circuits (adders, multiplexers, decoders) compute without remembering; sequential circuits (flip-flops, registers, disciplined by the clock) remember without computing. An ALU is adders and multiplexers choosing between operations; at this level of abstraction, a CPU can be thought of as an ALU plus registers and control logic, stepping through fetch-decode-execute on every clock edge.
We have now reached the processor: the next posts will move upward through memory, storage, and I/O, completing the picture of the machine before we leave hardware behind.