Computer Buses & Interconnects Explained

Every past post assumed one thing: parts can reach each other. Registers feed the ALU, the CPU reads memory, controllers deliver device data, all across wires. This post explains those wires. Not a PCIe manual, just what each road is for and what it costs.

Three buses: what, where, and when

A bus¹ is a set of wires between parts. The classic model splits it in three:

CPU -------- address bus (WHERE: which place?) ------> elsewhere
CPU <------> data bus (WHAT: the bytes) <------------> elsewhere
CPU -------- control lines (WHEN: read? write?) -----> elsewhere

The address bus² names the target: a memory spot or a device register. Its width sets reach: 32 bits name 4 GiB. The data bus carries the payload both ways: 64 bits move 8 bytes per trip. Control lines coordinate: read or write, size, clock, plus ready signals meaning data is valid now.

Where, what, when. That is the whole model.

Real example: mov rax, [0x2000] puts 0x2000 on the address bus, raises read on control, and grabs 8 bytes from the data bus.

CPU to memory: the fastest road

The CPU to memory path is the busiest road: every instruction and most data cross it, but caches save most trips. The talk is simple: put address out, signal read, collect bytes. Writes go in reverse.

Old machines shared one bus. New machines use dedicated point-to-point memory interconnects³: memory channels plus links like Infinity Fabric or Intel UPI in big servers, each moving tens of GB/s. Caches exist to avoid this travel: hits stay on chip, only misses pay for DRAM.

Real example: loop over a 1 MB array with a 12 MB cache and almost nothing leaves the chip. Jump across gigabytes at random and every miss waits tens of nanoseconds for DRAM.

CPU to devices: the I/O road

CPU to devices uses the same idea with slower timing. The CPU talks to controller registers with memory-mapped I/O⁴, where device registers just live at special addresses next to RAM. It writes a command like start read, the controller does the slow work alone, then signals done with an interrupt or a DMA copy into memory.

Speeds differ wildly. A keyboard needs almost nothing. A GPU or fast SSD needs gigabytes. Separate roads let each run at its own price.

Real example: type a letter and one interrupt carries one byte. Start a disk read and the controller moves megabytes by DMA while the CPU does other work.

PCIe: the general highway

PCI Express⁵ is the main I/O road inside modern boxes. It links processor to GPU, SSD, and network card with fast serial lanes. Each lane sends both ways at once. A x16 graphics slot has sixteen lanes, roughly sixteen times one lane. An NVMe SSD often uses four.

Two ideas matter without internals. Generations: each generation roughly doubles speed per lane, so ceiling depends on lane count times generation. Packets: unlike simple address plus data, PCIe wraps traffic in packets with headers and error checks, like tiny network messages inside the box. That lets one fabric serve GPU, storage, and network alike.

Real example: plug an NVMe SSD into a 4-lane slot. Sequential reads hit several GB/s because four lanes in parallel feed it. Move it to a 1-lane slot of an old generation and the same drive crawls.

SATA is the older storage road, capped near 0.5 GB/s. Computers keep it because HDDs use it: they are large mechanical drives with SATA plugs and cables, not cards that fit PCIe slots, and they remain the cheapest terabytes for backups and archives. Many SATA SSDs reuse the same plugs and cables.

USB: the road to the outside

If PCIe is the highway inside, Universal Serial Bus⁶ is the road out. It joins keyboards, mice, disks, and phones, carrying data plus power so small devices just work. Devices join a host controlled bus: the host schedules everything, peripherals stay simple.

History is generations keeping compatibility: megabits on USB 2.0, gigabits on USB 3.x, tens of gigabits on USB4. Plugs changed (Type-A, Micro, Type-C) but the flow stayed: plug in, identify, exchange packets. The port on the case is where an internal road changes medium.

Real example: plug a keyboard into USB-C. It reports it is a keyboard, the host polls it on schedule, key presses arrive as small packets. Same port, plug a disk, and bulk packets carry files plus charging power.

Bandwidth and latency: the cost of every road

Every road has two numbers. Bandwidth is flow per second: tens of GB/s per memory channel, GB/s on multi-lane PCIe, megabits to tens of gigabits on USB. Wider and faster raises it, sharing lowers each share.

Latency is trip time: single nanoseconds on chip, tens of nanoseconds to DRAM, microseconds across PCIe to a device, more over USB cables. Each border crossed adds delay, so urgent traffic stays on the shortest roads.

Bulk wants bandwidth. Start wants latency. DMA moves bulk without the CPU. Interrupts signal done without polling. Those two tricks from the I/O post are answers to these costs.

Real example: copy a 10 GB file and bandwidth rules. Click a mouse and latency rules: even tiny delay feels laggy.

The big picture

need: parts must reach each other
  ↓
model: address (where) + data (what) + control (when)
  ↓
CPU <-> memory (fastest, caches avoid trips)
CPU <-> devices (mapped addresses + interrupts + DMA)
  ↓
PCIe (inside highway, lanes and packets)
USB (outside road, host schedules, power plus data)
  ↓
price every road with bandwidth and latency

Every link answers where, what, and when. Old buses show it as wires, new links pack it into packets. The physical machine is now complete. The last post steps back to see the whole.

Footnotes

1. Bus (computing) - Wikipedia

2. Address bus - Wikipedia

3. Computer bus - Wikipedia

4. Memory-mapped I/O - Wikipedia

5. PCI Express - Wikipedia

6. USB - Wikipedia