Computer Buses & Interconnects Explained

Every previous post assumed something this one finally explains: the parts can reach each other. Registers hand values to the ALU, the CPU reads memory, controllers deliver device data, all across physical connections. This post answers one question: how do all these components actually communicate? We will look at the traditional three-bus model, the paths between CPU, memory, and devices, the interconnects between processors and memory themselves, the two standards you meet daily, and the bandwidth and latency of every road. This is not a PCIe internals manual; it stays at the level of the series: what each road is for and what it costs.

Three buses: what, where, and when

A bus¹ is a set of wires carrying signals between components. Conceptually, a traditional bus can be understood as three groups of signals:

CPU -------- address bus (WHERE: which location or device?) ------> elsewhere
CPU <------> data bus (WHAT: the bytes themselves) <--------------> elsewhere
CPU -------- control lines (WHEN/HOW: read? write? ready?) -------> elsewhere

The address bus² names the destination: a memory location or, on machines with port-mapped I/O, a device register. Its width sets how much can be named: 32 address bits can address 2^32 bytes, or 4 GiB; more bits reach further. The data bus carries the payload itself, in both directions; a 64-bit data path can carry 8 bytes per transfer. The control bus coordinates: read or write, transfer size, clocks, ready and acknowledge signals saying “data is valid now” and “received.”

Three roles: where, what, and when.

CPU ↔ memory: the fastest road

The CPU–memory path is the most demanding road in the machine: instructions and data ultimately depend on this path, but caches allow most accesses to avoid going all the way to DRAM. At this level of abstraction the conversation is simple: the CPU puts an address on the address bus, signals a read, and collects the arriving bytes from the data bus; writes run the exchange in reverse.

Physically this road has evolved from one shared bus into fast point-to-point memory interconnects³: dedicated memory channels and, in multi-socket systems, processor interconnects such as AMD’s Infinity Fabric or Intel’s UPI, carrying requests and data at tens of gigabytes per second per channel. Caches exist largely to spare this road: most accesses never leave the chip, and only misses pay the trip to DRAM. The memory post’s hierarchy is, seen from here, a strategy for avoiding travel.

CPU ↔ devices: the I/O road

Traffic between the CPU and devices follows the same basic idea with different timing. The processor reaches a controller’s registers through memory-mapped I/O⁴, where device registers simply occupy addresses in the same numbered space as RAM, then issues a command, and the controller performs the slow device work alone, later announcing completion with an interrupt or a DMA transfer straight into memory.

I/O has very different bandwidth and latency requirements from CPU–memory traffic. Some devices need relatively little bandwidth; others, such as GPUs and high-speed storage, need enormous amounts. Sharing one ultra-fast road for everything would waste its engineering. Separate roads let each run at its own economical speed.

PCIe: the general highway

The dominant I/O road in modern machines is PCI Express⁵: high-speed serial links connecting the processor to graphics cards, SSDs, network cards, and other peripherals. Each connection is made of lanes, and each lane uses a differential pair in each direction, allowing simultaneous transmission in both directions. A slot wired with sixteen lanes (x16) carries roughly sixteen times a single lane; an NVMe SSD typically uses four.

Two ideas make PCIe worth knowing without studying its internals. First, generations: each generation roughly doubles per-lane speed (tens of gigabits per second per lane in recent ones), so a card’s ceiling depends on both its lane count and its generation. Second, packets: unlike the simple “address plus data” memory conversation, PCIe traffic is packetized: requests and completions wrapped with headers, routing, and error checking, much like tiny network messages inside the machine. That packet discipline is what lets one fabric serve GPUs, storage, and networking alike.

USB: the road to the outside

If PCIe is the highway inside the box, Universal Serial Bus⁶ is the road out of it: the standard joining keyboards, mice, disks, cameras, and phones to the machine. USB combines data communication with power delivery, making it practical for peripherals such as keyboards, disks, cameras, and phones, and devices join a host-controlled bus where the host schedules transfers and coordinates communication, so peripherals stay simple while the controller does the coordination.

USB’s history reads as generations trading speed for compatibility: from megabits (USB 2.0) through gigabits (USB 3.x) to tens of gigabits (USB4), each generation keeping older devices working. The connector shapes changed (Type-A, Micro-USB, Type-C), while the underlying goal remained the same: connect peripherals through a standardized host-controlled interface. Plug in, get identified, start exchanging packets. The port on the case is simply where an internal I/O road changes medium.

Bandwidth and latency: the cost of every road

As with memory and storage, every road is described by two numbers. Bandwidth is how much flows per second: on the order of tens of gigabytes per second per memory channel, gigabytes per second for a multi-lane PCIe link, megabits to tens of gigabits for USB generations. Wider roads and faster clocks raise it; sharing it among passengers lowers each one’s share.

Latency is how long one trip takes: single-digit nanoseconds within the chip, tens of nanoseconds to DRAM, microseconds across PCIe to a device, and potentially higher latency for external USB peripherals. Each boundary crossed (chip edge, socket, cable) adds delay, which is why the hierarchy keeps urgent traffic on the shortest roads.

Bandwidth sets how fast bulk moves; latency sets how fast anything starts. DMA exists to move bulk data with minimal CPU involvement; interrupts let devices notify the CPU when something needs attention instead of forcing it to poll continuously. The two mechanisms from the I/O post are the machine’s adaptations to the costs laid out here.

The big picture

At the conceptual level, every connection solves the same problem: identify what is being communicated, where it belongs, and how the transfer is coordinated. Traditional buses make those roles explicit as address, data, and control signals; modern interconnects often encode them into packets. The CPU–memory path runs fastest because the instruction loop lives on it; memory interconnects and caches keep it fed; memory-mapped I/O extends the same addressing to devices; PCIe generalizes device traffic into packets over lanes; USB carries the conversation out of the box; and bandwidth plus latency price every road.

The physical machine is now complete: processor, logic, memory, storage, I/O, and the roads between them. The next and final post of the series steps back: the computer as a whole, how the layers compose, and where hardware ends and software begins.

Footnotes

1. Bus (computing) - Wikipedia

2. Address bus - Wikipedia

3. Computer bus - Wikipedia

4. Memory-mapped I/O - Wikipedia

5. PCI Express - Wikipedia

6. USB - Wikipedia