Memory Explained

September 5, 2026 • 6 min read

Table of contents

Memory cells: holding one bit
Addresses: every byte has a number
RAM: the workbench
ROM: memory that remembers
Three numbers: capacity, latency, bandwidth
The memory bus: talking to RAM
The memory hierarchy: fast, big, cheap, pick two
The big picture

The CPU post gave programs a place to run but nowhere to live: registers hold a few dozen values, and that is all. The digital logic post showed how a flip-flop holds one bit. This post scales that bit up to gigabytes.

Memory cells: holding one bit

Computer memory¹ starts from tiny structures that store bits, called memory cells. The machine needs billions of them, so one small design repeated billions of times decides everything.

There are two classic designs:

SRAM (Static RAM)²: a small loop that holds its bit steady while power is on. It uses about six transistors per bit, so it is fast and simple but large.
DRAM (Dynamic RAM)³: one transistor plus one tiny capacitor where the bit lives as charge. It is far smaller and cheaper, but the charge leaks in milliseconds, so the memory must refresh it again and again just to remember.

Think whiteboard versus leaky bucket. The whiteboard keeps your writing until you erase it. The bucket needs constant refilling.

Neither type wins on everything, so machines use both:

              SRAM                  DRAM
cell          loop, ~6              1 transistor +
              transistors           1 capacitor
size          large                 tiny
speed         very fast             slower
refresh       none needed           constant refresh
cost          expensive             cheap
used for      caches                main memory

SRAM buys speed with silicon area. DRAM buys density with refresh work. Architects put SRAM where speed matters most and DRAM where capacity matters most.

Real example: a few megabytes of SRAM cache sit next to the CPU. Gigabytes of DRAM sit further away as main memory.

Addresses: every byte has a number

A pile of cells is useless without names. That name is the memory address⁴, a number for each location, like a house number on a street. Modern memory is byte-addressable: each address names one byte, and bigger values use consecutive addresses.

With n address bits you can name 2^n places. 32 bits name 4 GiB. 64 bits could name far more than any machine holds, so real chips use fewer bits in practice.

Real example: a pointer in C like 0x7fff1000 is just such a house number. rsp from the CPU post is another address, pointing at the top of the stack.

RAM: the workbench

Random-access memory⁵ holds running programs and their data: code, heap, stack. Random access means any address can be read in about the same time. A tape must wind past everything before it, RAM just jumps straight there.

RAM is the CPU main partner: large enough for gigabytes of work, fast enough with caches helping, but forgetful. In its usual DRAM form it loses everything when power goes out.

Real example: unsaved work vanishes in a blackout for this reason. Every boot copies the operating system from storage into RAM again before anything can run.

ROM: memory that remembers

Read-only memory⁶ is the mirror image: it keeps its contents without power instead of being fast to rewrite. Its classic job is firmware, the first instructions on power-up, which must already be there before anything can load.

Pure read-only chips are history. Modern firmware lives in rewritable non-volatile memory⁷ like flash memory⁸. It keeps bits without power but can still be reprogrammed slowly in large blocks.

Real example: press the power button and the CPU starts running firmware from flash before your SSD or RAM is even ready. That code then starts the boot.

Three numbers: capacity, latency, bandwidth

Three numbers compare any memory:

Capacity: how much it holds. Registers hold bytes, caches hold kilobytes to megabytes, main memory holds gigabytes.
Latency: how long one access takes. Registers respond in a fraction of a nanosecond, fast caches in about a nanosecond, main memory in tens of nanoseconds⁹. Latency is the wait before the first byte arrives.
Bandwidth: how much arrives per second once flowing, in gigabytes per second. One memory channel moves tens of gigabytes per second. Bandwidth is the width of the pipe, latency is its length.

A sports car delivers one passenger quickly (low latency). A train delivers hundreds slowly (high bandwidth).

Real example: chasing a linked list pointer by pointer needs low latency. Streaming a video frame needs high bandwidth.

The memory bus: talking to RAM

Registers live inside the CPU, but main memory sits outside, so the processor reaches it through shared wires called the bus¹⁰:

CPU -------- address bus (which location?) -------> memory
CPU <------> data bus (the bytes themselves) <----> memory
CPU -------- control lines (read? write? when?) --> memory

To read, the CPU puts an address out, raises read, waits, and collects the bytes. A 64-bit data path moves 8 bytes per transfer. Modern DDR memory (DDR4, DDR5) transfers on both clock edges to double transfers per tick, but the talk stays the same: ask by address, answer with data.

Real example: mov rax, [0x1000] puts 0x1000 on the address bus, signals read, and rax receives the 8 bytes that come back on the data bus.

The memory hierarchy: fast, big, cheap, pick two

No single memory is fastest, largest, and cheapest at once, so machines stack them into a memory hierarchy¹¹:

registers     (bytes, fastest, program manages)
    ↓
caches        (KB to MB, ~1 ns, SRAM, hardware manages)
    ↓
main memory   (GB, tens of ns, DRAM)
    ↓
storage       (TB, microseconds to ms, non-volatile)

This works because of locality. Programs reuse the same data (temporal locality) and touch neighbors together (spatial locality). So hardware keeps copies of recent and nearby data in caches¹², where most accesses hit. A miss pays a trip down the ladder. Caches move whole 64-byte lines at once and track which copies are valid, all invisibly to your code.

Real example: a loop over an array for (i = 0; i < n; i++) sum += a[i] flies because each 64-byte cache line brings 16 integers at once and the next 15 are already there.

The big picture

cells       (SRAM / DRAM)
  ↓
addresses   (names for bytes)
  ↓
RAM         (work in progress) + ROM (remembers through power loss)
  ↓
bus         (ask by address, answer with data)
  ↓
hierarchy   (registers -> caches -> memory -> storage)

Cells hold bits, addresses name bytes, RAM hosts current work while ROM survives power loss, the bus carries the talk, and the hierarchy keeps what locality predicts the CPU will want next close by.

What the hierarchy pushes down is the next subject: the non-volatile world where data rests for years.

/tags

/sponsor

Enjoyed this post? You can sponsor me and this site.

/Related